Woodward's Diversity, Inclusion and Belonging Commitment At Woodward, no matter where you are from, your physical appearance, or how you identify, you deserve the opportunity to reach your greatest potential. We are on a journey to achieve this as an organization and want to work closely with our members to set the right path. We humbly acknowledge this will be an imperfe

Technical lead for high speed VLSI design in deep submicron FinFET processes. Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule. Solve design and tool problems requiring ground breaking approaches and champion innovation across the organization. Create technical presentations for peers and management. Gui

Duties WHAT IS THE INFORMATION TECHNOLOGY DIVISION? A description of the business units can be found at Twenty One (21) vacancies will be filled in the following specialty areas Anywhere within Information Technology. The following are the duties of this position at the full working level. If this vacancy includes more than one grade and you are selected at a lower grade

Provide successful Cache Architecture development and execution using RTL Design, Verilog HDL, and scripting. Collaborate with Cache and CPU Architects to design, document, and execute optimized high performance Cache and Routing Fabric designs. Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure. Collaborate with

As the Sr Product Owner you will own the team/sprint backlog and set priorities to deliver value based on customer roadmap and features for complex, higher value, and/or multiple products. Work with internal team members to ensure customer desires and business priorities are effectively communicated and reflected in the product backlog. Enable streamlined execution of pro

Digital Design SerDes Digital IP Design Engineer Oversees definition, design, verification co definition, and documentation for SerDes development. Performs architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and support for SerDes designs. Knowledge of all aspects of the process flow from high level RTL design to sy